A number of techniques exist for preparing such wafers. One example of one of the most effective current techniques for fabricating sSOI or SGOI type wafers is the production of an active layer of strained silicon (sSi) or relaxed SiGe by transfer thereof to an insulating support (for example a layer of SiO2 on a silicon substrate) using the Smart Cut® technique, to produce the desired heterostructure. Particular examples of implementations of such fabrication techniques are described in United States patent application US 2004/053477 and International patent application WO 2004/006311.
The finishing step of said wafers involves a selective etching and optional chemical-mechanical polishing procedure to eliminate the layer or layers subsisting above the silicon layer after transfer thereof to the “receiver” substrate and detachment from the “donor” substrate.
The term “selective etching” as used here means a chemical attack method which can selectively eliminate the upper layer of a given material (a layer of SiGe, for example) without attacking the next layer (strained silicon, for example), consequently termed a stop layer, by adjusting the composition of the chemical solution.
Because of the thinness of the active strained silicon layer (of the order of 200 angstroms (Å)), it is important to be able to control with great accuracy the thickness of said layer and the final surface quality. Such a requirement in the present case necessitates optimizing the selective etching procedure which is normally used.
For the usual method termed the “single wafer” method (since it processes wafers individually rather than collectively), selective etching is carried out by dispensing a chemical solution (CH3COOH/H2O2/HF mixture) directly over the surface of the wafer via a dispensing nozzle which is displaced from the center of the wafer over a radius of ±40% of the total radius while the wafer rotates, which causes non-uniform etching: the central portion of the wafer is more deeply etched than the edge (a phenomenon which is characterized by the term “edge-slow” for that type of etching).
In the same manner, polishing carried out prior to selective etching, for example by chemical-mechanical polishing (CMP) tends to etch the center more than the edges of the-wafers, as shown in FIGS. 1 and 2 which show the surface quality of an SiGe wafer after polishing and selective etching. In FIG. 1, the layer of SiGe 1 already has a “dish” shaped surface (SAP) after polishing alone, which is accentuated following selective etching (SAG). FIG. 2 shows the over etching which results at the center of the SiGe layer compared with the edges thereof.
When the wafer comprises a layer of strained silicon sSi beneath the superficial SiGe layer, the lack of etching uniformity (carried out directly or after polishing) causes over etching of the sSi layer located beneath the SiGe layer at the center of the wafer while SiGe residues remain at the edge of the wafer. Thus, it will be understood that concatenations of CMP and selective etching steps or selective etching alone cannot directly result in sufficient uniformity of thickness and roughness of the denuded sSi layer. This lack of uniformity is particularly noticeable with large diameter wafers such as 300 millimeter (mm) diameter wafers, for example.